In general, a device, e.g., a semiconductor IC device, capable of bidirectional communication with a host uses a signal frequency with standardized level for the bidirectional communication. Therefore, if the signal is not of the standard frequency, the communication cannot be established. Because of this, a technique for adjusting a signal frequency within a given standard frequency range has been available.
For example, Japanese Patent Laid-Open No. 2001-230750 discloses a frequency synchronization method, in which the frequency of the fundamental clock of an upstream transmitter and the frequency of the local clock of a downstream receiver are synchronized by controlling the frequency of the fundamental clock of the transmitter based on the frequency coordination information outputted from the receiver.
Japanese Patent Laid-Open No. 2001-244919 discloses a data transmitter transmitting/receiving data through an interface, in which a primary side data transmitter and a secondary side data transmitter have their own clock source and the secondary side reads out an amount of accumulated transmitting data to control a VCO frequency, thereby the clock of the secondary side is matched with the primary side clock.
Japanese Patent Laid-Open No. H11-284638 discloses a communication system to transmit and receive data without failure even if a local device system clock is not synchronized with an opposite-side system clock. To this end, an opposite-system clock included in a signal the local device system received is separated from data, the reception data is read out by a local device system clock, and the opposite-side system clock is used for a synchronizing signal for transmitting the transmission data.
Japanese Patent Laid-Open No. H09-270779 discloses a data synchronization system capable of synchronizing operation clocks between devices on transmission and reception sides without transmitting data synchronization clocks between the transmission side device and the reception side device. To this end, the reception side device controls the frequency of the operation clocks based on its own data residual amount.
Japanese Patent Laid-Open No. H08-335932 discloses a clock synchronization technique for synchronizing a transmission clock with a reception clock by controlling an oscillator with phase comparison information of a digital PLL circuit generating the reception clock, by controlling a frequency division ratio from received data.
A reference voltage generation circuit is disclosed in the document “CMOS Circuit Design, Layout, and Simulation”, by R. J. Baker, et al., (IEEE Press, p 480).